The silicon bipolar transistor has been the device of choice for many high power semiconductor device applications because bipolar transistors can be designed to handle relatively large current densities and support relatively high blocking voltages. However, despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications. First of all, bipolar transistors are current controlled devices which require relatively large base currents, typically one fifth to one tenth of the collector current, to maintain the transistor in an operating mode. Proportionally larger base currents can be expected for applications which also require high speed turn-off. Because of the large base current demands, the base drive circuitry for controlling turn-on and turn-off is relatively complex and expensive. Bipolar transistors are also vulnerable to premature breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications. Furthermore, it is relatively difficult to operate bipolar transistors in parallel because current diversion to a single transistor typically occurs at high temperatures, making emitter ballasting schemes necessary.
Insulated gate semiconductor devices, including the silicon power MOSFET, were developed, in part, to address this base drive problem. In a power MOSFET, the gate electrode provides turn-on and turn-off control upon the application of an appropriate gate bias. For example, turn-on in an N-type enhancement MOSFET occurs when a conductive N-type inversion layer is formed in the P-type body/channel region in response to the application of a positive gate bias. The inversion layer electrically connects the N-type source and drain regions and allows for majority carrier conduction therebetween. The power MOSFET's gate electrode is separated from the channel region by an intervening electrically insulating region comprising silicon dioxide (e.g., SiO.sub.2). Because the gate is insulated from the channel region, little if any gate current is required to maintain the MOSFET in a conductive state or to switch the MOSFET from an on-state to an off-state or vice-versa. The gate current is kept small during switching because the gate forms a capacitor with the MOSFET's channel region. Thus, only charging and discharging current ("displacement current") is required during switching. Because of the high input impedance associated with the insulated gate electrode, minimal current demands are placed on the gate and the gate drive circuitry can be easily implemented. Moreover, because current conduction in the MOSFET occurs through majority carrier transport only, the delay associated with the recombination and storage of excess minority carriers is not present. Accordingly, the switching speed of power MOSFETs can be made orders of magnitude faster than that of bipolar transistors.
Unlike bipolar transistors, power MOSFETs can be designed to withstand high current densities and the application of high voltages for relatively long durations, without encountering the destructive failure mechanism known as "second breakdown". Power MOSFETs can also be easily paralleled, because the forward voltage drop of power MOSFETs increases with increasing temperature, thereby promoting an even current distribution in parallel connected devices. Other MOS-gated power devices such as thyristors and insulated gate bipolar transistors can also take advantage of the benefits achieved by using insulated gate electrodes for controlling turn-on and turn-off.
For example, in the insulated gate bipolar transistor (IGBT), disclosed in an article, entitled "The Insulated Gate Transistor: A New Three terminal MOS Controlled Bipolar Power Device," IEEE Trans. Electron Devices, ED-31, pp. 821-828 (1984), on-state losses were shown to be greatly reduced when compared to power MOSFETs. This performance advantage was achieved because of conductivity modulation of the IGBT's drift region during the on-state. The operation of the IGBT can be described as follows with respect to the cross-sectional representation and electrical schematic shown in FIGS. 1A and 1B, respectively. In the reverse bias region, the anode is biased negative with respect to the cathode and the lower junction (J3) is reverse biased, thereby preventing conduction from the cathode to anode even though the upper junction (J2) is forward biased. This provides the device with its reverse blocking capability. In its forward blocking state when the anode is biased positive with respect to the cathode and the gate and cathode are electrically connected, the upper junction (J2) is reversed biased and conduction is prevented. If, however, a positive gate bias of sufficient magnitude is applied to the gate, the P-body region under the gate becomes inverted and the device operates in its forward conducting mode. In this mode of operation, electrons flow from the N.sup.+ source region into the N-drift region via the channel (inversion layer) under the gate. In addition, the lower junction (J3) is forward biased and the substrate P.sup.+ region injects holes (minority carriers) into the N-drift region. As the forward bias increases, the injected hole concentration increases until it exceeds the background doping level of the N-drift region. This high level minority carrier injection causes a conductivity modulation in the N-drift region and significantly reduces the IGBT's on-resistance.
As long as the gate bias is sufficiently large to produce enough charge in the inversion layer, the IGBT forward conduction characteristics will resemble those of a P-i-N diode. If the inversion layer conductivity is low, however, a substantial voltage drop across the channel will occur. To switch the IGBT from its forward conducting mode of operation to its reverse blocking mode requires the removal of the positive gate bias to thereby cut off the supply of electrons from the N.sup.+ source region to the N-drift region. Because of the high minority carrier concentration in the N-drift region, turn-off of the IGBT is not immediate, but instead is dependent on the minority carrier recombination lifetime in the N-drift region. Accordingly, the IGBT offers the potential for high forward conduction current density, full gate controlled transistor operation, low gate drive power requirements and reverse blocking capability providing directional power flow control.
One significant drawback to the operation of IGBTs at high current densities is the presence of the parasitic P-N-P-N structure between the anode and cathode which can cause a loss in the gate controlled turnoff capability. For example, as illustrated by FIG. 1B, the equivalent circuit for the IGBT of FIG. 1A includes a regenerative P-N-P-N path that can latch up if the lateral current in the P-body is sufficient to forward bias the P-body/N.sup.+ source junction. As will be understood by one skilled in the art, latch-up can be prevented so long as the sum of the current gains of the regeneratively coupled P-N-P and N-P-N transistors (.alpha..sub.pnp, .alpha..sub.npn) is less than unity. The shorting resistance R.sub.p (i.e., R.sub.p +R.sub.p+) in FIG. 1B represents the short circuit resistance between the P-body and emitter (N.sup.+ source) of the N-P-N transistor. The magnitude of R.sub.p is determined by the resistance of the P-body region underneath the N.sup.+ source, as illustrated in FIG. 1A. Because the current gain of the N-P-N transistor (.alpha..sub.npn) is directly dependent on the magnitude of R.sub.p, a small R.sub.p has been deemed essential for latch-up free operation at high forward current densities. When the P-body sheet resistance is kept low and/or the width or doping of the N.sup.+ source region is kept small, electron injection from the N.sup.+ source region to the P-body can be suppressed because the uppermost P-N junction between the P-body and N.sup.+ source is effectively short circuited, thereby eliminating the regenerative P-N-P-N path from between the anode and cathode. There are various processes that have been developed to reduce R.sub.p, including those described in articles entitled "Latch-back-free Self-Aligned Power MOSFET Structure with Silicided Source and Body Contact", IEEE Elec. Dev. Lett., Vol. EDL-9, No. 8, pp. 408-410 (1988); "SOL LIGBT Devices with a Dual P Well Implant for Improved Latching Characteristics", Proc. ISPSD, pp. 254-258 (1993); and "Latch-up Suppressed Insulated Gate Bipolar Transistor by the Deep P Ion Implantation under the N Source", Jpn. Jour. Appl. Phys., Vol. 33, pp. 563-565, No. 1B, January (1994).
However, as described in an article by J. P Russell, A. M. Goodman, L. A. Goodman and J. M. Neilson, entitled "The COMFET-A New High Conductance MOS-Gated Device", IEEE Electron Device Letters, Vol. EDL-4, No. 3, March (1983), pp. 63-65, even devices having a relatively low R.sub.p can be susceptible to latch-up if sufficiently large forward current densities cause significant emitter injection into the base of the N-P-N transistor and cause .alpha..sub.npn to increase. To reduce the likelihood of parasitic latch-up, the COMFET structure was modified to include a heavily doped P.sup.+ region in the middle of the P-body region, electrically connected to the cathode contact. To further lessen the magnitude of R.sub.p, an aluminum contact was also provided for shorting the N.sup.+ source regions to the P-body region.
FIG. 2 also illustrates a prior art IGBT embodying a trench which is formed after the lightly doped P-body and N.sup.+ source regions have been formed by double-diffusion techniques. However, as illustrated, much of the N.sup.+ source regions are still exposed to the relatively light doped body region which makes this device susceptible to parasitic thyristor latch-up. In addition, the N.sup.+ source doping was made relatively high, thereby increasing emitter efficiency, and the diffusion process is relatively complicated in order to maintain the heavily doped P.sup.+ region underneath the N.sup.+ emitter without a shift in threshold voltage. This device is described in an article by Morikawa et al., entitled "US-DMOS: A Novel Structure for Power MOSFETs", Vol. J75-C-2, No. 2, Jour. of IEIC, pp. 85-91, February (1992).
Thus, notwithstanding these attempts to limit the susceptibility of insulated gate semiconductor devices to parasitic bipolar transistor turn-on, the presence of the N.sup.+ source region in the P-body continues to pose a risk that under certain operating conditions parasitic bipolar transistor turn-on will occur and in the case of the IGBT cause parasitic thyristor latch-up. Furthermore, because many of the above described prior art IGBTs are not formed using self-alignment techniques and therefore require additional masking steps, the areas of the source region and body region may also be unnecessarily large to take into account photolithographic tolerances. This limits the degree to which these devices can be integrated as small unit cells for very high current applications.